Dual-Retention Synaptic Logic for Parallel Analog Computation with Reconfigurable Modes
발표자
김수현 (연세대학교)
연구책임자
조정호 (연세대학교)
초록
내용
We report a reconfigurable synaptic logic circuit that performs analog logic computation and parallel signal integration at the device level. By engineering the side chains of organic polymers, two synaptic transistors with distinct retention properties are designed: a long-term retention device for logic mode selection, and a short-term retention device for multi-input processing. These are integrated into a compact, dual-synapse logic gate capable of performing both AND and OR operations within a single structure. Demonstrated in a personalized disease risk assessment system, this architecture enables adaptive logic thresholds based on individual health conditions, offering efficient and low-power evaluation of biometric signals without complex circuitry.